Substrate fins with different heights

ABSTRACT

A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

BACKGROUND Background of the Invention

Multi-gate devices such as transistors may be formed on fin structures.The gate channel “width” of such a multi-gate device may depend at leastin part on the height of the fin.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional side view that illustrates a plurality offins of different heights on the same substrate.

FIG. 2 is a cross sectional side view that illustrates the substrate.

FIG. 3 is a cross sectional side view that illustrates the substrateafter isolation regions have been formed.

FIG. 4 is a cross sectional side view that illustrates a mask.

FIG. 5 is a cross-sectional side view that illustrates the patternedmask layer.

FIG. 6 is a cross-sectional side view that illustrates a time part waythrough an etching process that is used to form the fins.

FIG. 7 is a cross-sectional side view that illustrates another time partway through an etching process that is used to form the fins.

FIG. 8 is a cross-sectional side view that illustrates patterned masklayers that may be used to form fins having three different heights.

FIG. 9 is a cross-sectional side view that illustrates the finsresulting from the two different patterned mask layers illustrated inFIG. 8.

FIG. 10 is a cross-sectional side view that illustrates one applicationto which fins may be put: a multi-gate transistor.

FIG. 11 is an isometric view that illustrates the transistor.

FIGS. 12 and 13 are block diagrams that illustrate applications in whichthe above-mentioned NMOS and PMOS transistors may be used.

DETAILED DESCRIPTION

Various embodiments of a substrate having fins of different heights arediscussed in the following description. One skilled in the relevant artwill recognize that the various embodiments may be practiced without oneor more of the specific details, or with other replacement and/oradditional methods, materials, or components. In other instances,well-known structures, materials, or operations are not shown ordescribed in detail to avoid obscuring aspects of various embodiments ofthe invention. Similarly, for purposes of explanation, specific numbers,materials, and configurations are set forth in order to provide athorough understanding of the invention. Nevertheless, the invention maybe practiced without specific details. Furthermore, it is understoodthat the various embodiments shown in the figures are illustrativeexample representations and are not necessarily drawn to scale.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, material, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the invention, but do not denote that theyare present in every embodiment. Thus, the appearances of the phrases“in one embodiment” or “in an embodiment” in various places throughoutthis specification are not necessarily referring to the same embodimentof the invention. Furthermore, the particular features, structures,materials, or characteristics may be combined in any suitable manner inone or more embodiments. Various additional layers and/or structures maybe included and/or described features may be omitted in otherembodiments.

Various operations will be described as multiple discrete operations inturn, in a manner that is most helpful in understanding the invention.However, the order of description should not be construed as to implythat these operations are necessarily order dependent. In particular,these operations need not be performed in the order of presentation.Operations described may be performed in a different order, in series orin parallel, than the described embodiment. Various additionaloperations may be performed and/or described operations may be omittedin additional embodiments.

FIG. 1 is a cross sectional side view that illustrates a plurality offins 124 of different heights on the same substrate 102, according toone embodiment of the described invention. This substrate 102 maycomprise any material that may serve as a foundation upon which asemiconductor device may be built. In one example, substrate 102comprises silicon, although another material or other materials may beused in other examples. The substrate 102 may be a portion of a bulksubstrate, such as a wafer of single crystal silicon, asilicon-on-insulator (SOI) substrate 102 such as a layer of silicon on alayer of insulating material on another layer of silicon, a germaniumsubstrate 102, a group III-V material (such as GaAs, InSb, InAl, etc.)substrate 102, may be a substrate 102 comprising multiple layers, oranother type of substrate 102 comprising other material or materials.

Fins 124 have been formed on the substrate 102. Rather than all fins 124having the same height, the fins 124 have differing heights aboveisolation regions 104. Fins 124A through 124C have a smaller height 120while fins 124D through 124G have a larger height 122. This differencebetween heights 120 and 122 is selectable by choosing materials andetchants. In an embodiment, the greater height 122 is selected to bebetween a height roughly equal to the lower height 120 and a heightabout twice as great as the lower height 120 (i.e. height 120 is between99% and 50% of height 122). In another embodiment, the greater height122 may be more than twice the lower height 120. In an embodiment, thelower height 120 may be between 15-20 nanometers, and the greater height122 30-40 nanometers, although the invention is not limited to fins 124within those height ranges.

Such an ability to have fins 124 of different height allows multi-gatetransistors to be made on the fins 124 with different desiredproperties. As the drive current of a transistor is dependent on thegate channel “width” of a multi-gate transistor, and the “width” may bemade greater by use of a taller fin 124 without increasing the area ofthe transistor, selectable multi-height fins 124 allow the transistorswith the same area to have selected drive currents based on the finheights. In other embodiments, different areas of transistors may beselected without changing drive currents by selecting the fin heights.Rather than having one selectable parameter, transistor area, with whichto affect drive currents, designers may independently select transistorheight and area to achieve desired device characteristics.

FIGS. 2 through 9 are cross sectional side views that illustrate howfins 124 of different heights on the same substrate 102 may be formedaccording to one embodiment.

FIG. 2 is a cross sectional side view that illustrates the substrate102. As discussed above, the substrate 102 may comprise any materialthat may serve as a foundation upon which a semiconductor device may bebuilt.

FIG. 3 is a cross sectional side view that illustrates the substrate 102after isolation regions 104 have been formed. These isolation regions104 may be, for example, shallow trench isolation regions. Any suitablemethod for forming isolation regions 104 may be used, and the isolationregions 104 may comprise any suitable material. A suitable isolationregion 104 material is one that may be selectively etched while leavingthe substrate 102 material substantially intact. In one embodiment, theisolation regions 104 comprise a silicon oxide material and thesubstrate 102 comprises silicon. Other suitable isolation regionmaterials include, for example, silicon dioxide (which may be depositedin a variety of processes), and spin-on glass (SOG), among others.

The formation of the isolation regions 104 also results in pre-finregions 106 of the substrate 102. These pre-fin regions 106 are betweenthe isolation regions 104.

FIG. 4 is a cross sectional side view that illustrates a mask layer 108formed on the substrate 102, isolation regions 104, and pre-fin regions106. The mask layer 108 may be formed from a material that has an etchrate in a selected etchant within an order of magnitude of the etch rateof the isolation regions 104 in the selected etchant in one embodiment.In some embodiments, the mask layer 108 has an etch rate faster than theisolation regions 104 in the selected etchant. In some embodiments, themask layer 108 has an etch rate that is twice the etch rate of theisolation regions 104 or less in the selected etchant. In someembodiments, the mask layer 108 has an etch rate that is one half theetch rate of the isolation regions 104 or more in the selected etchant.In one embodiment, the mask layer 108 comprises a silicon nitridematerial substantially free from oxygen and carbon. In otherembodiments, the mask layer 108 may comprise a silicon nitride materialwith various amounts of oxygen and/or carbon present to modulate theetch rate, a SiC material, or other materials may also be used.

FIG. 5 is a cross-sectional side view that illustrates the patternedmask layer 110. Any suitable method may be used to pattern the masklayer 108 of FIG. 4 to result in the patterned mask layer 110. Thepatterned mask layer 110 remains over pre-fin regions 106A-106C, toprotect them from part of the etching to come. Pre-fin regions 106D-106Gare unprotected by the patterned mask layer 110. This will result inpre-fin regions 106A-106C becoming fins 124A-124C having a smallerheight 120 than the height of fins 124D-124G that stem from pre-finregions 106D-106G.

FIG. 6 is a cross-sectional side view that illustrates the patternedmask layer 110, the pre-fin regions 106, the isolation regions 104, andthe substrate 102 part way through an etching process that is used toform the fins 124. In FIG. 6, part of the patterned mask layer 110 hasbeen removed, leaving remaining partial mask layer 114. Thickness 116 ofthe patterned mask layer 110 has been removed. Also, a thickness 112 ofthe isolation regions 104 has been removed at this point in the etchingprocess. The difference between thickness 112 and thickness 116 willdepend upon the difference between the etch rates of mask layer 108 andisolation regions 104. In an embodiment where the mask layer 108comprises a silicon nitride material, the isolation regions 104 comprisea silicon oxide material, and the substrate 102 and pre-fin regions 106comprise silicon, the etchant chosen may be a hydrofluoric acid (HF).Different etchants and/or different materials may be used, selectedbased on the desired etchant rate difference between the mask layer 108and the isolation regions 104, and the etch selectivity to etch the masklayer 108 and isolation regions 104 while leaving the substrate 102 andpre-fin regions 106 substantially intact. For example, spin-ondielectric films such as silicate or siloxane can be used as the masklayer 108 or the isolation regions 104, with HF or buffered HF as theetchant. Other combinations may also be used.

FIG. 7 is a cross-sectional side view that illustrates the pre-finregions 106, the isolation regions 104, and the substrate 102 at anothertime part way through an etching process that is used to form the fins124. At the point illustrated in FIG. 7, all of the patterned mask layer110 has been removed, and the isolation regions 104A-104C formerlyprotected by the patterned mask layer 110 are about to be etched. Atthis point, a thickness 118 of isolation regions 104E-104G, plus theportion of isolation region 104D adjacent pre-fin region 106D, have beenremoved. This thickness 118 sets the height differential (height 122minus height 120) between the taller fins 124D-124G of FIG. 1, and theshorter fins 124A-124C of FIG. 1 (subject to small variations of theetching process). Thus, the thickness and etch rate of the material ofthe patterned mask layer 110 is chosen to provide the desired thickness118, and the desired height differential between the fins 124 of FIG. 1.The etching process will continue after the point illustrated in FIG. 7to remove portions of isolation regions 104A-104C and more of isolationregions 104D-104G and result in the fins 124 of FIG. 1.

FIG. 1, as mentioned above, is a cross sectional side view thatillustrates differently-heighted fins 124 resulting from the masking andetching has continued past the point illustrated in FIG. 7 to removeportions of isolation regions 104A-104C, plus the left side of isolationregion 104D, to form fins 124A-124C with a desired height 120. Thiscontinued etching has also removed more of isolation regions 104E-104G,plus the right side of isolation region 104D, to form fins 124D-124Gwith desired height 122. The mask layer 108 thickness is chosen based onthe desired height differential 118 and the etch rate difference betweenthe material of the mask layer 108 and the material of the isolationregions 104. The etch time is selected to etch through the patternedmask layer 110 and remove portions of isolation regions 104A-104C, plusthe left side of isolation region 104D, to result in desired height 120of fins 124A-124C.

FIG. 8 is a cross-sectional side view that illustrates patterned masklayers 126, 128 that may be used to form fins 124 having three differentheights. Isolation regions 104F, 104G, and the right side of isolationregion 104E are not covered by a mask layer. Patterned mask layer 126has been patterned to cover isolation regions 104A-104D, plus the leftside of isolation region 104E. Patterned mask layer 128 has beenpatterned to cover isolation regions 104A-104C, plus the left side ofisolation region 104D. When an etching process is performed, isolationregions 104F, 104G, and the right side of isolation region 104E will beetched from the start of the process. The right side of isolation region104D and the left side of isolation region 104E will be etched after adelay caused by time it takes to remove patterned mask layer 126.Finally, the left side of isolation region 104D and isolation regions104A-104C will be etched after a longer delay caused by the time ittakes to remove both patterned mask layer 128 and patterned mask layer126.

FIG. 9 is a cross-sectional side view that illustrates the fins 124resulting from the two different patterned mask layers 126, 128illustrated in FIG. 8. Because they were not covered by a mask layer,pre-fin regions 106E-106G became the fins 124E-124G with the greatestheight 134. Because it was covered by only one patterned layer 126,pre-fin region 106D became fin 124D with a middle height 132. Becausethey were covered by two patterned mask layers 126, 128, pre-fin regions106A-106C became fins 124A-124C with the shortest height 130.

The thickness of patterned mask layer 126 is selected based on thedesired height differential between fin 124D and fins 124E-124G (i.e.height 134 minus height 132) and the etch rate difference between thematerial of the mask layer 126 and the material of the isolation regions104. Similarly, the thickness of patterned mask layer 128 is selectedbased on the desired height differential between fins 124A-124C and fin124D (i.e. height 132 minus height 130) and the etch rate differencebetween the material of the mask layer 128 and the material of theisolation regions 104.

Additional mask layers may be used to make yet other differences in theheights of fins 124 on a substrate. More than three different heightsmay be created. Rather than multiple stacked patterned mask layers 126,128, there may be a first patterned mask layer with a first thicknesscovering some pre-fin regions 106, and a second patterned mask layerwith a second thickness greater than the first thickness coveringdifferent pre-fin regions 106 than those covered by the first patternedmask layer. Alternatively, mask layers with different etch rates in anetchant may be used in place of, or in addition to, differentthicknesses. No matter how many different heights are present in thefinal set of fins 124, the resulting fins 124 may be used in anyapplication calling for such structures.

FIG. 10 is a cross-sectional side view that illustrates one applicationto which fins 124 may be put: a multi-gate transistor 135. Theillustrated embodiment of the multi-gate transistor 135 is a tri-gatetransistor 135 that includes the fin 124 adjacent the isolation regions104. There is a gate dielectric layer 136 adjacent the fin 124, and agate electrode 138 adjacent the gate dielectric layer 136. As the gateelectrode 138 is adjacent three sides of the fin 124, the gate channel“width” of the transistor 135 includes the fin 124 width 140 plus twicethe fin 124 height 142 (this is why the term channel “width” as usedherein has quotations; the “width” is not merely the width of thechannel, but also includes other dimensions). As the drive current ofthe transistor 124 is at least partially dependent on the gate channel“width” of the transistor 135, the drive current may be increased byincreasing the height 142 while leaving the other dimensions of thetransistor 135 the same.

FIG. 11 is an isometric view that illustrates the transistor 135. Asmentioned above, because the gate channel “width” is dependent on theheight 142 of the fin 124, the drive current of the transistor 135 maybe increased without increasing the fin 124 width 140 or the gate depth144. This means that by increasing the height 142 of the fin 124, thedrive current may be increased without the transistor 135 taking up morearea. “Area” referring to area within the X-Y plane; note that in FIGS.1-10, the X-axis goes from left to right in the plane of the picture,the Z-axis is up and down in the plane of the picture, and the Y-axis isnormal to the plane of the picture. Thus, using the embodimentillustrated in FIG. 1, fins 124A-124C may be used to make multi-gatetransistors 135 with lower drive current and fins 124D-124G used to makemulti-gate transistors 135 with higher drive current, with the areas ofeach of the multi-gate transistors (in the X-Y plane) beingsubstantially the same.

One application is to make NMOS (n-type metal oxide semiconductortransistors) and PMOS (p-type metal oxide semiconductor transistors)having substantially the same drive current while being closer in areacompared to NMOS and PMOS transistors made on fins having equal heights.A PMOS transistor having the same gate channel “width” as an NMOStransistor will typically have a lower drive current. By increasing thefin 124 height 142 of the PMOS transistor compared to the NMOStransistor on the same substrate 102, the PMOS gate “width” can beincreased, and the drive current increased, without increasing the areataken up by the PMOS transistor. Thus, the PMOS and NMOS transistors 135on a substrate 102 may have substantially the same area andsubstantially the same drive current.

In other embodiments, the PMOS transistor 135 may have substantially thesame area as the NMOS transistor 135 and the drive current of the PMOStransistor may be more or less than that of the NMOS transistor byselecting the fin heights of the respective transistor types.Alternatively, both the area and fin height 142 of the PMOS transistormay be selected to each be greater or less than the NMOS transistorbased on the desired drive current for some specific circuit requirementand acceptable use of area on the substrate 102.

In yet other embodiments, the drive current of multiple instances of asingle transistor type (either N- or P-type) may be varied across asingle substrate 102 without changing their area by having different fin124 heights 142. This may be useful, for example, when transistors 135of the same area are desired (e.g. when design rules that dictatespacing of transistors are based on transistor area) yet different drivecurrents are desired. The area and height of the fin 124 may each beseparately chosen by the device designer to result in a device such as atransistor having the desired drive current and area.

FIGS. 12 and 13 are block diagrams that illustrate applications in whichthe above-mentioned NMOS and PMOS transistors 135 may be used. FIG. 12includes a die 150 and a memory cell 148 that is part of the die 150.The memory cell 148, which may be, for example, a SRAM cell 148,includes a number of both NMOS and PMOS multi-gate transistors 135. ThePMOS transistors 135 have a taller fin 124 than the NMOS transistors 135so that transistors 135 of both types have substantially the same areaand substantially the same drive current. FIG. 13 includes a die 150 anda ring oscillator 152 that is part of the die 150. The ring oscillator152 includes a number of both NMOS and PMOS multi-gate transistors 135.The PMOS transistors 135 have a taller fin 124 than the NMOS transistors135 so that transistors 135 of both types have substantially the samearea and substantially the same drive current. Numerous other examplesof devices and circuits that would benefit from transistors 135 withdifferent height 142 fins 124 are also possible.

The foregoing description of the embodiments of the invention has beenpresented for the purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. This description and the claims following include terms, suchas left, right, top, bottom, over, under, upper, lower, first, second,etc. that are used for descriptive purposes only and are not to beconstrued as limiting. For example, terms designating relative verticalposition refer to a situation where a device side (or active surface) ofa substrate or integrated circuit is the “top” surface of thatsubstrate; the substrate may actually be in any orientation so that a“top” side of a substrate may be lower than the “bottom” side in astandard terrestrial frame of reference and still fall within themeaning of the term “top.” The term “on” as used herein (including inthe claims) does not indicate that a first layer “on” a second layer isdirectly on and in immediate contact with the second layer unless suchis specifically stated; there may be a third layer or other structurebetween the first layer and the second layer on the first layer. Theembodiments of a device or article described herein can be manufactured,used, or shipped in a number of positions and orientations. Personsskilled in the relevant art can appreciate that many modifications andvariations are possible in light of the above teaching. Persons skilledin the art will recognize various equivalent combinations andsubstitutions for various components shown in the Figures. It istherefore intended that the scope of the invention be limited not bythis detailed description, but rather by the claims appended hereto.

1-12. (canceled)
 13. A semiconductor device, comprising: a substrate; afirst multi-gate transistor on a first portion of the substrate, thefirst multi-gate transistor comprising a first fin, the first fin havinga first height above a first isolation region; and a second multi-gatetransistor on a second portion of the substrate, the second multi-gatetransistor comprising a second fin, the second fin having a secondheight above a second isolation region, the second height being greaterthan the first height.
 14. The device of claim 13, wherein the firstmulti-gate transistor is an N-type transistor and the second multi-gatetransistor is a P-type transistor.
 15. The device of claim 14, furthercomprising a memory cell, wherein both the first and second multi-gatetransistors are transistors of the memory cell.
 16. The device of claim14, further comprising a ring oscillator, wherein both the first andsecond multi-gate transistors are transistors of the ring oscillator.17. The device of claim 14 wherein the second height is greater than thefirst height in an amount great enough that the drive current of thefirst transistor is within 10% of the drive current of the secondtransistor.
 18. The device of claim 17 wherein first multi-gatetransistor has a first area, the second multi-gate transistor has asecond area, and the first area is within about 15% of the second area.19. The device of claim 13 wherein the second height is at least 25%greater than the first height.
 20. The device of claim 13, furthercomprising a third multi-gate transistor on a third portion of thesubstrate, the third multi-gate transistor comprising a third fin, thethird fin having a third height above a third isolation region, thethird height being greater than the second height.